In manufacturing and employing semiconductor devices, it is important that the devices operate properly. When a completed semiconductor device malfunctions after it has been installed in a finished product, such as a consumer electronics product, the malfunction of the semiconductor device may cause the entire product to fail. That is, the malfunction of a single semiconductor device may cause an entire consumer electronics device to function improperly. Most semiconductor devices are formed using a number of material layers. Each layer is patterned to add or remove selected portions to form circuit features that will eventually make up a complete integrated circuit. Because problems encountered in the formation of any one layer may render an entire device unusable, defective devices are therefore tested to physically locate defects. One goal of testing devices it to identify individual devices which may have a defect, while a secondary goal is to help to troubleshoot device processes.
One type of semiconductor device is a programmable logic device, such as a complex programmable logic device (CPLD) or a field programmable gate array (FPGA), which is designed to be user-programmable so that users may implement logic designs of their choices. In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream into configuration memory cells of the FPGA. As circuit designs implemented in an FPGA have become more complex, the number of CLBs, IOBs, and/or other resources (such as multiplexers and block RAMs) has increased, as well as the routing resources to make the connections between the various blocks. Accordingly, programmable logic devices are one group of integrated circuits which particularly benefit from testing. Test programs for FPGAs typically consist of many paired test patterns including one to configure the FPGA, and another to test the functionality of the FPGA after configuration. Because the circuits implemented by different customers using programmable logic devices are generally unique, a test may be specific to the elements used by the implemented circuit. In some cases, a circuit design may undergo modifications during a product development phase. Thus, multiple versions of a circuit may be implemented on an FPGA, requiring multiple tests of the circuit.
Test equipment typically has limitations in testing a device under test (DUT), such as an FPGA. The maximum number of test patterns which will fit into a scan memory is loaded at the beginning of a test operation, and then the test equipment applies the test patterns to one or more devices mounted on the test equipment. While device test coverage is increased with the application of more test patterns, test equipment is also limited by its operating frequency. As more test patterns are required to adequately test the increasingly complex designs, the time required to test the designs has significantly increased. Although it is possible to use test equipment which runs at a higher operating frequency, it is often prohibitively costly to upgrade existing test equipment to operate at a higher frequency or replace test equipment with faster test equipment.
Accordingly, there is a need for a method of and circuit for decreasing the time required to test an integrated circuit.